Searching for authors named "Andreas Dandalis" – sorted by Relevance.
10 documents found, showing 1 through 10.
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Run-time Mapping of Graph-Problem Instances onto Reconfigurable Hardware
- …this paper we demonstrated a case-study solution that achieves 6 orders of magnitude speedup over the stateof -the art for mapping graph-problem instances onto FPGAs. The novelty of our approach is that the mapping process performs an incremental adaptation of problemspecific configurations to the i…
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A Parallel Pipelined SAT Solver for FPGA's
- …. Solving Boolean satisability problems in recongurable hardware is an area of great research interest. Originally, recongurable hardware was used to map each problem instance and thus exploit maximum parallelism in evaluation of variable assignments. However, techniques to greatly reduce the se…
- Cited by 2 (1 self) – Add To MetaCart
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Efficient Self-Reconfigurable Implementations Using On-Chip Memory
- …This paper 16:7ns O(ne) O(e)…
- Cited by 2 (0 self) – Add To MetaCart
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Space-efficient Mapping of 2D-DCT onto Dynamically Configurable Coarse-Grained Architectures
- …. This paper shows an efficient design for 2D-DCT on dynamically configurable coarse-grained architectures. Such coarse-grained architectures can provide improved performance for computationally demanding applications as compared to fine-grained FPGAs. We have developed a novel technique for derivin…
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Fast Parallel Implementation of DFT Using Configurable Devices
- …. In this paper we propose a fast parallel implementation of Discrete Fourier Transform (DFT) using FPGAs. Our design is based on the Arithmetic Fourier Transform (AFT) using zero-order interpolation. For a given problem of size N , AFT requires only O(N 2 ) additions and O(N) real multiplication…
- Cited by 9 (7 self) – Add To MetaCart
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Mapping Homogeneous Computations onto Dynamically Configurable Coarse-Grained Architectures
- …this paper we show a methodology for deriving dynamic computation structures for 2 dimensioned homogeneous computations. Homogeneous computations lead to all PEs having the same functionality. The derived dynamic structures match the datapath-oriented nature of coarse-grained architectures and lead …
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Domain Specific Mapping for Solving Graph Problems on Reconfigurable Devices
- …. Conventional mapping approaches to Reconfigurable Computing (RC) utilize CAD tools to perform the technology mapping of a high-level design. In comparison with the execution time on the hardware, extensive amount of time is spent for compilation by the CAD tools. However, the long compilation time…
- Cited by 9 (4 self) – Add To MetaCart
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Run-time Performance Optimization of an FPGA-based Deduction Engine for SAT Solvers
- …FPGAs are a promising technology for accelerating SAT solvers. Besides their high density, fine granularity, and massive parallelism, FPGAs provide the opportunity for run-time customization of the hardware based on the given SAT instance. In this paper, a parallel deduction engine is proposed fo…
- Cited by 3 (0 self) – Add To MetaCart
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A Comparative Study of Performance of AES Final Candidates Using FPGAs
- …In this paper we study and compare the performance of FPGA-based implementations of the #ve #- nal AES candidates #MARS, RC6, Rijndael, Serpent, and Two#sh#. FPGAs seem to match extremely well with the operations required by the #nal candidates. Among the various time-space implementation tradeo #s,…
- Cited by 17 (0 self) – Add To MetaCart
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An Adaptive Cryptographic Engine for IPSec Architectures
- …Architectures that implement the Internet Protocol Security (IPSec) standard have to meet the enormous computing demands of cryptographic algorithms. In addition, IPSec architectures have to be flexible enough to adapt to diverse security parameters. This paper proposes anFPGAbased Adaptive Cryptogr…
- Cited by 13 (1 self) – Add To MetaCart
Showing 1 through 10.
