Searching for authors named "Anand Raghunathan" – sorted by Relevance.
51 documents found, showing 1 through 10.
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Communication Architecture Tuners: A Methodology for the Design of High-Performance Communication Architectures for System-on-Chips
- … Architectures for System-on-Chips yKanishka Lahiri zAnand Raghunathan zGanesh Lakshminarayana ySujit Dey y…
- Cited by 22 (3 self) – Add To MetaCart
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Design Space Exploration for Optimizing On-Chip Communication Architectures
- …, Anand Raghunathan, and Sujit Dey Abstract—Rapid growth in the complexity of system-on-chips is being…
- Cited by 21 (1 self) – Add To MetaCart
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LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs
- …Kanishka Lahiri zAnand Raghunathan zGanesh Lakshminarayana yDept. of Electrical and Computer Engg., UC San Diego…
- Cited by 18 (0 self) – Add To MetaCart
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Battery-Driven System Design: A New Frontier in Low Power Design
- …Battery-Driven System Design: A New Frontier in Low Power Design ? yKanishka Lahiri zAnand…
- Cited by 28 (2 self) – Add To MetaCart
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Efficient Exploration of the SoC Communication Architecture Design Space
- … was supported by NEC USA Inc., and by the California Micro Program Anand Raghunathan NEC USA C&C Research Labs…
- Cited by 22 (1 self) – Add To MetaCart
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Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures
- … Architectures * Kanishka Lahiri Anand Raghunathan Sujit Dey Dept. of ECE NEC USA C&C Research Labs, Dept. of ECE…
- Cited by 23 (0 self) – Add To MetaCart
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Design of High-Performance System-on-Chips using Communication Architecture Tuners
- …Kanishka Lahiri zAnand Raghunathan zGanesh Lakshminarayana ySujit Dey yDept. of Electrical and Computer Engg…
- Cited by 6 (0 self) – Add To MetaCart
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Communication Architecture Based Power Management for Battery Efficient System Design
- …, Louisiana, USA. Copyright 2002 ACM 1-58113-461-4/02/0006 ...$5.00. Anand Raghunathan C&C Research Labs NEC…
- Cited by 9 (1 self) – Add To MetaCart
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Verification of rtl generated from scheduled behavior in a high-level synsthesis flow
- … Subhrajit Bhattacharya Anand Raghunathan Akira Mukaiyama C&C Research Labs, NEC USA, Princeton, NJ Abstract…
- Cited by 4 (1 self) – Add To MetaCart
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Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation
- … Pranav Ashar Anand Raghunathan Aarti Gupta Subhrajit Bhattacharya C&C Research Laboratories, NEC USA…
- Cited by 1 (0 self) – Add To MetaCart
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