Searching for authors named "Amit Narayan" – sorted by Relevance.
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Measurement and Modeling of MOS Transistor Current Mismatch in Analog IC's
- Measurement and Modeling of MOS Transistor Current Mismatch in Analog IC's Eric Felt Amit Narayan
- Cited by 9 (1 self) – Add To MetaCart
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Formal Verification of Combinational Circuits
- Formal Verification of Combinational Circuits Jawahar Jain 1 Amit Narayan 2 M. Fujita 1 A
- Cited by 7 (0 self) – Add To MetaCart
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Improved Symbolic Verification Using Partitioning Techniques
- 1,3 , Christian Stangier 1 , Amit Narayan 1 , and Jawahar Jain 1 1 Fujitsu Laboratories of America
- Cited by 11 (7 self) – Add To MetaCart
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Wireplanning in Logic Synthesis
- Abstract Wireplanning in Logic Synthesis Wilsin Gosti Amit Narayan + Robert K. Brayton Alberto L
- Cited by 13 (2 self) – Add To MetaCart
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Steady-state analysis of voltage and current controlled oscillators
- , David C Lee and Amit Narayan Berkeley Design Automation, Santa Clara CA 95054 Abstract— This paper
- Cited by 2 (2 self) – Add To MetaCart
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A Partitioning Methodology for BDD-based Verification
- , Jawahar Jain 3 , Christian Stangier 3 , Amit Narayan, David L. Dill 1 , and E. Allen Emerson 2 1 Stanford
- Cited by 9 (4 self) – Add To MetaCart
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Wilsin Gosti
- Wilsin Gosti Wireplanning in Logic Synthesis * Amit Narayan + Robert K. Brayton Alberto L
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