Searching for authors named "Alireza Hodjat" – sorted by Relevance.

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14 documents found, showing 1 through 10. Next 10 →

Interfacing a High Speed Crypto Accelerator to an Embedded CPU
by Alireza Hodjat — 2004 — in Proceedings of the 38th Asilomar Conference on Signals, Systems, and Computers
…Interfacing a High Speed Crypto Accelerator to an Embedded CPU Alireza Hodjat ahodjat @ee…
Cited by 5 (0 self) – Add To MetaCart

A hyperelliptic curve crypto coprocessor for an 8051 microcontroller
by Alireza Hodjat, David Hwang — 2005 — In Proceedings of The IEEE 2005 Workshop on Signal Processing Systems (SIPS’05
…A Hyperelliptic Curve Crypto Coprocessor for an 8051 Microcontroller Alireza Hodjat, David Hwang…
Cited by 2 (1 self) – Add To MetaCart

A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA
by Alireza Hodjat And — 2004
… calculation of the values must be implemented in logic. Rijmen Alireza Hodjat and Ingrid Verbauwhede…
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Minimum Area Cost for a 30 to 70 Gbits/s AES Processor
by Alireza Hodjat And — 2004
… technology. However, the area cost will increase very much. Therefore, a pipelined Alireza Hodjat and Ingrid…
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Architectural Design Features of a Programmable High Throughput AES Coprocessor
by Alireza Hodjat, Patrick Schaumont, Ingrid Verbauwhede — 2004 — AES Coprocessor, in the proceedings of ITCC 2004, vol 2, pp 498-502, Las Vegas
…Architectural Design Features of a Programmable High Throughput AES Coprocessor Alireza Hodjat…
Cited by 3 (0 self) – Add To MetaCart

Embedded software integration for coarse-grain reconfigurable architectures
by Patrick Schaumont, Kazuo Sakiyama, Alireza Hodjat, Ingrid Verbauwhede — 2004 — In Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004
… Sakiyama, Alireza Hodjat, Ingrid Verbauwhede Electrical Engineering Department University of California…
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Area-throughput trade-offs for fully pipelined 30 to 70 Gbits/s AES processors
by Alireza Hodjat, Student Member, Ingrid Verbauwhede, Senior Member — IEEE Transactions on Computers
…-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors Alireza Hodjat, Student Member, IEEE, and Ingrid…
Cited by 1 (0 self) – Add To MetaCart

Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051 µP
by Lejla Batina, Alireza Hodjat, Bart Preneel, Ingrid Verbauwhede — 2005 — Proceedings of 7th International Workshop on Cryptographic Hardware and Embedded Systems (CHES), number 3659 in Lecture Notes in Computer Science
… Batina 2 ,DavidHwang 1 , Alireza Hodjat 1 , Bart Preneel 2 , and Ingrid Verbauwhede 1,2 1 University…
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Speed-Area Trade-off for 10 to 100 Gbits/s
by Throughput Aes Processor, Alireza Hodjat — 2003 — 37 th Asilomar Conference on Signals, Systems, and Computers
…Speed-Area Trade-off for 10 to 100 Gbits/s Throughput AES Processor Alireza Hodjat ahodjat @ee…
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Streaming Encryption for a Secure Wavelength and Time Domain Hopped Optical Network
by Herwin Chan, Alireza Hodjat, Jun Shi, Richard Wesel, Ingrid Verbauwhede — 2004 — Proc. IEEE Intl Conf. Information Technology (ITCC 2004
…, Alireza Hodjat, Jun Shi, Richard Wesel, Ingrid Verbauwhede {herwin, ahodjat, junshi, wesel, ingrid} @ ee…
Cited by 1 (1 self) – Add To MetaCart

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