Searching for authors named "Ali Keshavarzi" – sorted by Relevance.
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248 Design for Testability DFT for Delay Fault Testing of High-Performance Digital Circuits
- to the long-term reliability of future digital ICs. These problems have motivated us to investigate Ali
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Parametric Timing Failures and Defect-based Testing
- Hawkins, Ali Keshavarzi*, Jaume Segura** Abstract Parametric failures have been with us since
- Cited by 2 (0 self) – Add To MetaCart
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Burn-in temperature projections for deep sub-micron technologies
- Vassighi, Manoj Sachdev, Ali Keshavarzi * , and C.F. Hawkins ** Electrical and Computer Engineering Dept
- Cited by 1 (1 self) – Add To MetaCart
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CMOS IC technology scaling and its impact on burn-in
- , Ali Keshavarzi, and Chuck Hawkins Abstract—This article describes how CMOS IC technology scaling
- Cited by 1 (0 self) – Add To MetaCart
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Parameter variations and impact on circuits and microarchitecture
- Karnik, Siva Narendra, Jim Tschanz, Ali Keshavarzi, Vivek De Circuit Research, Intel Labs, JF3-334, 2111
- Cited by 61 (1 self) – Add To MetaCart
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Technology Scaling Behavior of Optimum Reverse Body Bias for Standby Leakage Power Reduction
- in CMOS IC's Ali Keshavarzi, Siva Narendra, Shekhar Borkar, Charles Hawkind, Kaushik Roy* and Vivek De
- Cited by 9 (0 self) – Add To MetaCart
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Design optimizations for microprocessors at low temperature
- 2.1 Design Optimizations for Microprocessors at Low Temperature Arman Vassighi, Ali Keshavarzi
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