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8,103 documents found, showing 1 through 10. Next 10 →

A Clock Distribution Network for Microprocessors
by Phillip J. Restle, Timothy G. Mcnamara, David A. Webber, Peter J. Camporese, Kwok F. Eng, Keith A. Jenkins, Senior Member, David H. Allen, Michael J. Rohn, Michael P. Quaranta, David W. Boerstler, Charles J. Alpert, Craig A. Carter, Roger N. Bailey, John G. Petrovick, Byron L. Krauter, Bradley D. Mccredie — 2001 — IEEE Journal of Solid-State Circuits
…792 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 5, MAY 2001 A Clock Distribution Network…
Cited by 17 (0 self) – Add To MetaCart

Initial Experiences With a Clock Synchronisation Test Bed
by P Ashton, J Mackenzie — 1999
…Initial experiences with a clock synchronisation test bed P Ashton and J Mackenzie, Department…
Cited by 1 (1 self) – Add To MetaCart

A Clock Distribution Scheme for Large RSFQ Circuits
by Krzysztof Gaj, Eby G. Friedman, Marc J. Feldman, Andrzej Krasniewski — 1995 — IEEE Trans. Appl. Supercond
…A Clock Distribution Scheme for Large RSFQ Circuits Krzysztof Gaj, Eby G. Friedman, and Marc J…
Cited by 7 (7 self) – Add To MetaCart

Evaluating a clock synchronization for dependable sensor networks
by Spiro Trikaliotis, Georg Lukas — 2006 — In Proceedings of the 20th IEEE International Parallel and Distributed Processing Symposium
…Evaluating a Clock Synchronization for Dependable Sensor Networks Spiro Trikaliotis 1 , Georg…
Cited by 4 (3 self) – Add To MetaCart

19.5 A Clock Skew Absorbing Flip-Flop
by Nikola Nedovic, Vojin G. Oklobdzija, William W. Walker
…ISSCC 2003 / SESSION 19 / PROCESSOR BUILDING BLOCKS / PAPER 19.5 19.5 A Clock Skew Absorbing Flip…
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The Design of a Clock Synchronization Sub-system for Parallel Embedded Systems
by M. Fleury, A. C. Downton, A. F. Clark, H. P. Sava — 1997 — IEE Proceedings Part E (Computers and Digital Techniques
…The Design of a Clock Synchronization Sub-system for Parallel Embedded Systems M. Fleury, A. C…
Cited by 5 (5 self) – Add To MetaCart

A Clock Power Model to Evaluate Impact of Architectural and Technology Optimizations
by David E. Duarte, N. Vijaykrishnan, Mary Jane Irwin — 2002 — IEEE Transactions on VLSI Systems
… 2002 A Clock Power Model to Evaluate Impact of Architectural and Technology Optimizations David E…
Cited by 11 (0 self) – Add To MetaCart

Analysis of Random Jitter in a Clock Multiplying DLL Architecture
by R.C.H. van de Beek, E. A. M. Klumperink, C. S. Vaucher, B. Nauta — 2001
…Analysis of Random Jitter in a Clock Multiplying DLL Architecture R.C.H. van de Beek , E.A…
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A clocked denotational semantics for Lucid-Synchrone in COQ
by Sylvain Boulmé, Grégoire Hamon — 2001
…A clocked denotational semantics for Lucid-Synchrone in Coq Sylvain Boulme Gregoire Hamon…
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A Clock and Trail Model for Somite Formation, Specialization and Polarization
by Michel Kerszberg-Lewis, Lewis Wolpert — 2000
…://www.idealibrary.com on A Clock and Trail Model for Somite Formation, Specialization and Polarization MICHEL KERSZBERG…
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