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Searching for "A 10-Gbps" – sorted by Relevance.

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117 documents found, showing 1 through 10. Next 10 →

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A 10-Gbps full-AES crypto design with a twisted BDD S-box architecture
by Sumio Morioka, Akashi Satoh — 2004 — IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2002
…A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture Sumio Morioka and Akashi…
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A 10-Gbps High-Speed Single-Chip Network Intrusion Detection and Prevention System
by N. Sertac Artan, Rajdip Ghosh, Yanchuan Guo, H. Jonathan Chao
…A 10-Gbps High-Speed Single-Chip Network Intrusion Detection and Prevention System N. Sertac Artan…
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Fast, Large-Scale String Match for a 10Gbps Fpga-Based Network Intrusion
by Ioannis Sourdis, Dionisios Pnevmatikatos — 2003 — FPL
…Fast, Large-Scale String Match for a 10Gbps FPGA-based Network Intrusion Detection System Ioannis…
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ATLAS II: Optimizing a 10Gbps Single-Chip ATM Switch
by Dionisios Pnevmatikatos, George Kornaros — 1999 — Proc. IEEE Intl. ASIC/SOC Conf
…ATLAS II: Optimizing a 10Gbps Single-Chip ATM Switch Dionisios Pnevmatikatos and George Kornaros…
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Experimental Results on the Simultaneous Transmission Of Two 2.5 Gbps Optical-CDMA Channels and a
by Stefano Galli, Ron Menendez, Paul Toliver, Thomas Banwell, Janet Jackel, Jeff Young, Shahab Etemad, J. Young, S. Etemad — 2005
… Optical-CDMA Channels and a 10 Gbps OOK Channel Within the Same WDM Window S. Galli, R. Menendez, P…
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A new look at Ethernet: Experiences from 10 Gigabit
by Ethernet End-To-End Network, Antony Antony, Johan Blom, Freek Dijkstra, Cees Laat — 2003
… workstations on each side equipped with a 10 Gbps network interface card. The maximum throughput obtained from…
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Snort offloader: A reconfigurable hardware nids filter
by Haoyu Song, Todd Sproull, Mike Attig, John Lockwood — 2005 — in 15th International Conference on Field Programmable Logic and Applications (FPL 2005
… of malicious content passing over a 10Gbps network using FPGA hardware that operates with 10 Gbps of throughput…
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Architecture and Hardware for Scheduling Gigabit Packet Streams
by Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten Schwan, Richard West — 2002 — Stanford University
… Ethernet frames on a 1 Gbps link and 1500byte Ethernet frames on a 10 Gbps link. ,4 running hardware…
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Parallel Packet Switching using Multiplexors with Virtual Input Queues
by Ahmed Aslam And
… such as iSLIP [10]. Scaling a switch matrix scheduling algorithm to 10-Gbps line speed and a large number…
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Approved by: DESIGN OF CMOS INTEGRATED PHASE-LOCKED LOOPS FOR MULTI-GIGABITS SERIAL DATA LINKS
by Shanfeng Cheng, P. Soriaga — 2006
…. Secondly, a 10 Gbps clock and data recovery (CDR) chip for SONET OC- 192, the mainstream standard…
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