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280
Dual Voltage Design for Minimum Energy Using
"... Abstract—This paper presents a new slack-time based algorithm for dual Vdd design to achieve maximum energy saving. Although a global optimum is sought computation time is kept low. The slack of a gate is defined as the difference between the critical path delay for the circuit and the delay of the ..."
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. For c880, the energy saving is 22 % for subthreshold voltage operation and 50 % for nominal operation in PTM CMOS 90nm. For c2670 nominal voltage design, time of dual voltage optimization is reduced 44X compared to the MILP method. This new algorithm is beneficial for a large circuits with many large
• Table 7-14: Corrected OOB Nominal Threshold Voltage sub-table for
"... UG198 (v3.0) October 30, 2009Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, ..."
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UG198 (v3.0) October 30, 2009Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display
Nominated Lecture THE MECHANICS OF INSTRUMENTATION
"... In this lecture instrumentation will be interpreted as the ways and means to transport and modify signals SO as to make them suitable for the input channels of human beings and automatic controllers. A difference may be made between measuring and control systems; the first present the value of the m ..."
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to be measured to another physical dimension, more suited for transport or evaluation. Typical are the conver-sions to electric voltages, pneumatic or hydraulic pressures. The main requirements for the design of a transducer are a low energy consumption from the measuring source, fast response and low
SSTA Design Methodology for Low Voltage Operation
, 2010
"... Statistical process variations have long been an important design issue. But until recently, process variations have been global process variations, i.e., transistor pa-rameters may vary from die to die but are constant within a die. With transistor geometries shrinking below 65nm, however, a new ki ..."
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. At these voltages, the stochastic delay resulting from local variations has standard deviation comparable to the nominal delay. In order to predict the statistical impact of local variations on circuit performance, it is necessary to develop the statistical models that accurately reflect local variations
Pinch-off Voltage
"... DESCRIPTION The MwT-5 is a dual gate GaAs MESFET device whose nominal quarter-micron gate length and 300 micron gate width make it ideally suited to applications requiring high-gain in the 500 MHz to 26 GHz frequency range. The straigth gate geometry of the MwT-5 makes it equally effective for eithe ..."
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DESCRIPTION The MwT-5 is a dual gate GaAs MESFET device whose nominal quarter-micron gate length and 300 micron gate width make it ideally suited to applications requiring high-gain in the 500 MHz to 26 GHz frequency range. The straigth gate geometry of the MwT-5 makes it equally effective
Analysis of transfer touch voltages in low-voltage electrical installations
"... Protection against electric shock in our homes and work places is one of the most important priorities for electrical services engineers who are now designing electrical installations to conform to the requirements of the 17th edition IEE Wiring Regulations (BS7671: 2008). Now Chapter 41 of BS7671: ..."
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analysis in relation to the design parameters that are being used by designers and installers. Based on the results of a real case study, it appears that there is sufficient evidence to show that it may not be sufficiently safe to use the nominal external earth fault loop impedance quoted
Control Method for Low-Voltage DC Power Supply
- IEEE Power Electronics Specialists Conference
, 1997
"... Abstract { The paper describes a control method for operating a variable switching frequency buck converter, designed to convert an input battery voltage of 4.5 to 8Vdc to an output voltage of 3.3Vdc with a maximum load current of 4Adc. The advantages of the control method are that the output voltag ..."
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Cited by 10 (2 self)
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Abstract { The paper describes a control method for operating a variable switching frequency buck converter, designed to convert an input battery voltage of 4.5 to 8Vdc to an output voltage of 3.3Vdc with a maximum load current of 4Adc. The advantages of the control method are that the output
Evaluation of Voltage Interpolation to Address Process Variations
"... Abstract — Post-fabrication tuning provides a promising design approach to mitigate the performance and power overheads of process variation in advanced fabrication technologies. This paper explores design considerations and VLSI-CAD support for a recently proposed postfabrication tuning knob called ..."
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Cited by 4 (3 self)
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called voltage interpolation. The paper discusses design tradeoffs between circuit tuning range and static power overheads that can be performed within the synthesis flow of the design process. The paper explores the scheme for a 64-core chip-multiprocessor machine using industrial-grade design blocks
Energy-Efficient Dual-Voltage Design Using Topological Constraints
, 2013
"... We propose a method for dual supply voltage digital design to reduce energy consumption without violating the given performance requirement. Although the basic idea of placing low voltage gates on non-critical paths is well known, a new two-step procedures does it so more efficiently. First, given a ..."
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We propose a method for dual supply voltage digital design to reduce energy consumption without violating the given performance requirement. Although the basic idea of placing low voltage gates on non-critical paths is well known, a new two-step procedures does it so more efficiently. First, given
Characterizing the Voltage Scaling Limitations of Razorbased Designs. Workshop on Energy Effective Design held in conjunction with ISCA
, 2009
"... Worst-case processor designs have high yields, but are expensive in terms of area and power. Better-than-worst-case designs like Razor allow processors to be designed for the average case and still maintain high yields. One benet that is often claimed about better than worst-case designs like Razor ..."
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Cited by 6 (1 self)
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is that they allow low-power processing, as the processors can now be run at voltages signicantly lower than their nominal input volt-age. In this paper, we show that the power benets of Razor due to voltage scaling are greatly determined by the design of the circuit it is trying to protect. We show that the benets
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