Results 1 - 10 of 285

A Compiler-Assisted Approach to SPMD Execution

by Ron Cytron Jim, Jim Lipkis T, Edith Schonberg T - In Proceedings of Supercomputing '90 , 1990
"... Today, two styles of scientific parallel programming prevail. In the SPMD style, all processors execute the same program, with sequential code executed redundantly and parallel code executed cooperatively. ..."
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Today, two styles of scientific parallel programming prevail. In the SPMD style, all processors execute the same program, with sequential code executed redundantly and parallel code executed cooperatively.

Implementing MAC protocols for cooperative relaying: A compiler-assisted approach

by Hermann S. Lichte, Stefan Valentin - In Proceedings of the 1st international conference on Simulation tools and techniques for communications, networks and systems (SIMUTools , 2008
"... Evaluating the performance of a cooperative relaying protocol requires an implementation for simulators and/or software-defined radios (SDRs) with an appropriate model for error detection, combining, and Medium Access Control (MAC) automaton. Such implementations are essential for meaningful evaluat ..."
Abstract - Cited by 7 (2 self) - Add to MetaCart
that are inherent to all cooperative relaying protocols, and we propose a new language for their specification. Then, we show how to construct a compiler for the proposed language that generates most of the required implementation (model and MAC automaton) automatically. This approach prevents subtle mistakes

Compiler-assisted multiple instruction retry

by Chung-chi Jim Li, Shyh-kwei Chen, W. Kent Fuchs, Wen-mei W. Hwu - Coordinated Science Laboratory, University of Illinois , 1991
"... This paper describes a compiler-assisted approach toproviding multiple instruction rollback capability for general purpose processor registers. The objective isachieved by having the compiler remove all forms of N-instruction anti-dependencies. Pseudo register anti-dependencies are removed by loop p ..."
Abstract - Cited by 14 (4 self) - Add to MetaCart
This paper describes a compiler-assisted approach toproviding multiple instruction rollback capability for general purpose processor registers. The objective isachieved by having the compiler remove all forms of N-instruction anti-dependencies. Pseudo register anti-dependencies are removed by loop

Compiler-assisted Full Checkpointing

by Chung-chi Jim Li, Elliot M. Stewart, W. Kent Fuchs , 1994
"... This paper describes a compiler-based approach to checkpointing for process recovery. The implementation is transparent to both the programmer and the hardware. The compiler-generated sparse potential checkpoint code maintains the desired checkpoint interval. Adaptive checkpointing reduces the size ..."
Abstract - Cited by 17 (2 self) - Add to MetaCart
of the checkpoints. Training is used to select low-cost, high-coverage potential checkpoints. The problem of selecting potential checkpoints is shown to be NP-complete, and a heuristic algorithm is introduced that determines a quick suboptimal solution. These compiler-assisted checkpointing techniques have been

AD-A256 039 COMPILER-ASSISTED STATIC CHECKPOINT INSERTION 1

by Junsheng Long, W. Kent, Fuchs Jacob, A. Abraham , 1992
"... This paper describes a compiler-assisted approach for static checkpoint insertion. Instead of fixing the checkpoint location before program execution, a compiler enhanced polling mechanism is utilized to maintain both the desired checkpoint intervals and reproducible checkpoint loca-tions. The techn ..."
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This paper describes a compiler-assisted approach for static checkpoint insertion. Instead of fixing the checkpoint location before program execution, a compiler enhanced polling mechanism is utilized to maintain both the desired checkpoint intervals and reproducible checkpoint loca

AD-A246 496iii IN 111111111 I W UllN COMPILER-ASSISTED STATIC CHECKPOINT INSERTION'

by Junsheng Long, W. Kent, Fuchs Jacob, A. Abraham
"... This paper describes a compiler-assisted approach for static checkpoint insertion. Instead of fixing the checkpoint location before program execution, a compiler enhanced polling mechanism is utilized to maintain both the desired checkpoint intervals and reproducible checkpoint loca-tions. The techn ..."
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This paper describes a compiler-assisted approach for static checkpoint insertion. Instead of fixing the checkpoint location before program execution, a compiler enhanced polling mechanism is utilized to maintain both the desired checkpoint intervals and reproducible checkpoint loca

Compiler-Assisted Preferred Caching for Embedded Systems with STT-RAM based Hybrid Cache

by Qingan Li, Mengying Zhao, Chun Jason Xue, Yanxiang He
"... As technology scales down, energy consumption is becoming a big problem for traditional SRAM-based cache hierarchies. The emerging Spin-Torque Transfer RAM (STT-RAM) is a promis-ing replacement for large on-chip cache due to its ultra low leak-age power and high storage density. However, write opera ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
to dynami-cally move write-intensive data from STT-RAM to SRAM. These techniques lead to extra overheads. In this paper, we propose a compiler-assisted approach, preferred caching, to significantly re-duce the migration overhead by giving migration-intensive memory blocks the preference for the SRAM part

BRANCH RECOVERY WITH COMPILER-ASSISTED MULTIPLE INSTRUCTION RETRY

by W. -m. Hwu
"... In processing systems where rapid recovery from transient faults is important, schemes for multiple instruction rollback recovery may be appropriate. Multiple instruction retry has been implemented in hardware by researchers and also in mainframe computers. This paper extends compiler-assisted instr ..."
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In processing systems where rapid recovery from transient faults is important, schemes for multiple instruction rollback recovery may be appropriate. Multiple instruction retry has been implemented in hardware by researchers and also in mainframe computers. This paper extends compiler-assisted

Improving Power Efficiency with Compiler-Assisted Cache Replacement

by Hongbo Yang, R. Govindarajan, Guang R. Gao, Ziang Hu
"... Abstract — Data cache in embedded systems plays the roles of both speeding up program execution and reducing power consumption. However, a hardware-only cache management scheme usually results in unsatisfactory cache utilization. In several new architectures, cache management details are accessible ..."
Abstract - Cited by 3 (0 self) - Add to MetaCart
. In such an architecture, what-to-lock and when-to-lock are important issues to achieve good cache performance. To this end, this paper gives a 0/1 knapsack problem formulation, which can be efficiently solved using a dynamic programming algorithm. We implemented this formulation in the MIPSpro compiler and our approach

Reducing Context Switch Overhead with Compiler-Assisted Threading

by Jarmo Takala, Heikki Kultala
"... Multithreading is an important software modularization technique. However, it can incur substantial overheads, es-pecially in processors where the amount of architecturally visible state is large. We propose an implementation technique for co-operative multithreading, where context switches occur in ..."
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in places that minimize the amount of state that needs to be saved. The subset of processor state saved during each con-text switch is based on where the switch occurs. We have validated the approach by an empirical study of resource usage in basic blocks, and by implementing the co-operative threading
Results 1 - 10 of 285