number of iterations. Hierarchical reduction comple-ments the software pipelining technique, permitting a consis-tent performance improvement be obtained. The techniques proposed have been validated by an im-plementation of a compiler for Warp, a systolic array consist-ing of 10 VLIW processors

schedule for such a program is a function which assigns an execution date to each action. Knowledge of such a schedule allows one to estimate the intrinsic degree of parallelism of the program and to compile a parallel version for multiprocessor architectures or systolic arrays. This paper deals

This paper presents the New Systolic Language as a general solution to the problem systolic programming. The language provides a simple programming interface for systolic algorithms suitable for di erent hardware platforms and software simulators. The New Systolic Language hides the details

effectively exploit massive parallelism in computationally intensive applications. With advances in VLSI, WSI, and FPGA technologies, they have progressed from fixedfunction to generalpurpose architectures. hen Sun Microsystems introduced its first workstation, the company could not have imagined how quickly workstations would revolutionize computing. The idea of a community of engineers, scientists, or researchers time-sharing on a single mainframe computer could hardly have become ancient any more quickly. The almost instant wide acceptance of workstations

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those reported previously. In general, the technique can be used to design bounded broadcast systolic arrays for algorithms whose implementation can benefit from broadcasting. Keywords: all-pairs shortest distance, broadcast, data dependence, parallel computation, recurrence equation, systolic array

RNA structure prediction, or folding, is a computeintensive task that lies at the core of several search applications in bioinformatics. We begin to address the need for high-throughput RNA folding by accelerating the Nussinov folding algorithm using a 2D systolic array architecture. We adapt

power. The major applications in image processing systems may be divided into few categories; pre-processing, coding, compression, restoration, segmentation, representation, description and interpretation. Introducing the systolic arrays into the area of image processing can significantly improve speed

of Laguerre expansions, although the Laguerre expansion of a discrete sequence can be represented as a network. Thus the purpose of this paper is to propose a systolic array implementation for Laguerre expansions. 2 Laguerre Expansions Given a sequence x(n), its Laguerre expansion is defined as [4],[5] x

We show how the refinement calculus, combined with the action system formalism gives a stepwise refinement method for deriving parallel convolution algorithms that model systolic computation. We inspect how different architectural designs influence the derivation process. The action systems