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Table 2: Metric-space of metrics ordered by

in Categories and Subject Descriptors
by Abram Hindle, Michael W. Godfrey
"... In PAGE 2: ... In this paper we show that indentation metrics can be used as a proxy for complexity. Table2 shows where our metrics fit in within the space of other metrics. This table orders metrics by their level of language and semantic awareness.... ..."

Table 2. Contemporary RISC processors features

in unknown title
by unknown authors

Table 2.1: Peak mega#0Dops and memory bandwidth

in Evaluation And Exploitation Of Locality In The Data Driven Execution Model
by William Marcus Miller

Table 6: Cache organizations studied

in Memory Subsystem Performance of Programs Using Copying Garbage Collection
by Amer Diwan, David Tarditi, Eliot Moss 1994
"... In PAGE 7: ... Explorationof more exotic memory subsystem features is left to future work. Table6 summarizes the cache organizations simulated. Table 7 lists the memory subsystem organization for some popular machines.... ..."
Cited by 41

Table-cache cache

in by
by Fujian Liu

Table 1. Instruction-level measurements on the index server.

in unknown title
by unknown authors
"... In PAGE 5: ... The main activity in the index server consists of decoding compressed information in the inverted index and finding matches against a set of documents that could satisfy a query. Table1 shows some basic instruction-level measurements of the index server program running on a 1-GHz dual- processor Pentium III system. The application has a moderately high CPI, considering that the Pentium III is capable of issuing three instructions per cycle.... In PAGE 6: ... The avail- able thread-level parallelism should allow near-linear speedup with the number of cores, and a shared L2 cache of reasonable size would speed up interprocessor communication. Memory system Table1 also outlines the main memory sys- tem performance parameters. We observe good performance for the instruction cache and instruction translation look-aside buffer, a result of the relatively small inner-loop code size.... ..."

Table 1. Instruction-level measurements on the index server.

in AMENABLE TO EXTENSIVE PARALLELIZATION, GOOGLE’S WEB SEARCH APPLICATION LETS DIFFERENT QUERIES RUN ON DIFFERENT PROCESSORS AND, BY PARTITIONING THE OVERALL INDEX, ALSO LETS A SINGLE QUERY USE MULTIPLE PROCESSORS. TO HANDLE THIS WORKLOAD, GOOGLE’S ARCHITECT
by Luiz André Barroso, Jeffrey Dean, Urs Hölzle, Superior Performance, At A Fraction, Of The, Cost Of, A System Built
"... In PAGE 5: ... The main activity in the index server consists of decoding compressed information in the inverted index and finding matches against a set of documents that could satisfy a query. Table1 shows some basic instruction-level measurements of the index server program running on a 1-GHz dual- processor Pentium III system. The application has a moderately high CPI, considering that the Pentium III is capable of issuing three instructions per cycle.... In PAGE 6: ... The avail- able thread-level parallelism should allow near-linear speedup with the number of cores, and a shared L2 cache of reasonable size would speed up interprocessor communication. Memory system Table1 also outlines the main memory sys- tem performance parameters. We observe good performance for the instruction cache and instruction translation look-aside buffer, a result of the relatively small inner-loop code size.... ..."

Table VI. Memory-system organizations studied

in Memory-System Performance of Programs with Intensive Heap Allocation
by Amer Diwan, David Tarditi, Eliot Moss 1995
Cited by 15

Table 1: Average Network Messages per Call Setup

in Efficient PCS Call Setup Protocols
by Yingwei Cui, Derek Lam, Jennifer Widom, Donald C. Cox 1998

Table / Cache

in Trace-driven Memory Simulation: A Survey
by Richard A. Uhlig, Trevor N. Mudge 1997
Cited by 128
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